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So I produced a file for paint.net:\u00a0www.hertell.nu\/webfiles\/A3640.pdn<\/a><\/p>\n That could look like with one layer enabled:<\/p>\n <\/p>\n This helped me alot. as I could write a small excel-document containing a list of all ICs with all active pins and where to check for\u00a0continuity, this shorted the time to check traces:<\/p>\n This file is downloadable here:\u00a0www.hertell.nu\/webfiles\/A3640TraceTerminations.xlsx<\/a><\/p>\n Where every IC have its own tab. cells marked in grey are terminationpoints of each pin. if you only follow all grey cells. you have checked every trace on the board without checking one double trace.<\/p>\n Anyway, this still was a quite slow process. especially when I was unable to check any specific via or so. So being one week on a businesstrip I decided to do the backtrace again, this time I have found a Electronics CAD program that allowed me to use a scanned picture as background. It is not the best program in the world, but it works.<\/p>\n This software is called Sprint-Layout, downloadable at:\u00a0http:\/\/www.abacom-online.de\/uk\/html\/sprint-layout.html<\/a>\u00a0 there are a demoversion, with it you can view files, edit but not print, export or save.<\/p>\n Anyway. \u00a0now the BIG thing!..<\/p>\n <\/p>\n This is how my file looks like.. \u00a0And I guess you want it? \u00a0SURE! \u00a0\u00a0www.hertell.nu\/webfiles\/A3640-CAD.zip<\/a><\/p>\n This is free for you to use. \u00a0you can either buy the software or use the testversion to point on any via and see where it goes. \u00a0I would recomend you to use the “test” function as it is a very nice feature.<\/p>\n BUT! I will not recomend you to produce any PCBs out of this, vias can be too close, traces too close etc. and inner layers (GND\/VCC) are just actually made to show that they are connected. no real designthinking behind it. \u00a0it will be too thin traces, badly connected or so. So simple: you are on your own.<\/p>\n <\/p>\n When you have checked all traces. \u00a0there is sometimes issues with the GALs.<\/p>\n So the original GAL files can be downloaded from:\u00a0www.hertell.nu\/webfiles\/A3640.zip<\/a><\/p>\n There is also a hack to remove 2 waitstates improving memoryspeed. this CAN be instable if you use a quaddoubler. but works fine with 040-060 adaptes. (or 040) <\/p>\n Anyway. \u00a0enjoy this and hope you have good use if this. It was a hard thing and a very aching back but helpful for me and hopefully for all of you out there.<\/p>\n <\/p>\n UPDATE!!<\/p>\n I have now did a tidy up. and changes. .so that is why I do not change the original files.<\/p>\n So I continued my project some and did take a dead A3640 board with heavy leakge. \u00a0SANDED off all print and scanned it and got:<\/p>\n Top: Bottom: I checked traces so they wasn’t too close (hopefully) and drillholes. Still GND\/VCC planes might be SHIT! I am no hw designer. but hopefully it will WORK!<\/p>\n NOW I ordered some PCBs..<\/p>\n This is a render of the order:<\/p>\n <\/p>\n Lets hope it all works.<\/p>\n If you want the gerbers or the sprint file for this:<\/p>\n www.hertell.nu\/webfiles\/A3640Rev33.zip<\/a><\/p>\n Board arrived. and looks ABSOLUTLEY GREAT!<\/span><\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n
\nHack is made by speedgeek and can be downloaded from:\u00a0www.hertell.nu\/webfiles\/A3640_ST_MOD.zip<\/a><\/p>\n
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\nalso I did some changes doing the delay line hack so you can overclock the board.
\nAdding possability of having both types of oscillators. adding some text etc.<\/p>\n<\/a><\/p>\n