The Commodore A3640 is a very simple 68040 accelerator for the Amiga 3000 and 4000 made only to be low priced.
So no memory onboard etc.
BUT as they also populated the card with 3 electrolyte capacitors with the wrong polarity, many of them have died due to leakage.
The most common problem is that there are a via that have gone bad due to the leakage. And I have been annoyed that it is kind of hard to follow traces.
So last summer. I did the painful thing of finding 2 scanned pictures of a bare A3640 board and in paint.net I followed every single trace and documented it.
This resulted in a picturefile with several layers where I have marked all signals of all chips and where it terminates so I can with a voltmeter check if a trace is ok or not.
The pictures I used was:
So I produced a file for paint.net: www.hertell.nu/webfiles/A3640.pdn
That could look like with one layer enabled:
This helped me alot. as I could write a small excel-document containing a list of all ICs with all active pins and where to check for continuity, this shorted the time to check traces:
This file is downloadable here: www.hertell.nu/webfiles/A3640TraceTerminations.xlsx
Where every IC have its own tab. cells marked in grey are terminationpoints of each pin. if you only follow all grey cells. you have checked every trace on the board without checking one double trace.
Anyway, this still was a quite slow process. especially when I was unable to check any specific via or so. So being one week on a businesstrip I decided to do the backtrace again, this time I have found a Electronics CAD program that allowed me to use a scanned picture as background. It is not the best program in the world, but it works.
This software is called Sprint-Layout, downloadable at: http://www.abacom-online.de/uk/html/sprint-layout.html there are a demoversion, with it you can view files, edit but not print, export or save.
Anyway. now the BIG thing!..
This is how my file looks like.. And I guess you want it? SURE! www.hertell.nu/webfiles/A3640-CAD.zip
This is free for you to use. you can either buy the software or use the testversion to point on any via and see where it goes. I would recomend you to use the “test” function as it is a very nice feature.
BUT! I will not recomend you to produce any PCBs out of this, vias can be too close, traces too close etc. and inner layers (GND/VCC) are just actually made to show that they are connected. no real designthinking behind it. it will be too thin traces, badly connected or so. So simple: you are on your own.
When you have checked all traces. there is sometimes issues with the GALs.
So the original GAL files can be downloaded from: www.hertell.nu/webfiles/A3640.zip
There is also a hack to remove 2 waitstates improving memoryspeed. this CAN be instable if you use a quaddoubler. but works fine with 040-060 adaptes. (or 040)
Hack is made by speedgeek and can be downloaded from: www.hertell.nu/webfiles/A3640_ST_MOD.zip
Anyway. enjoy this and hope you have good use if this. It was a hard thing and a very aching back but helpful for me and hopefully for all of you out there.
I have now did a tidy up. and changes. .so that is why I do not change the original files.
So I continued my project some and did take a dead A3640 board with heavy leakge. SANDED off all print and scanned it and got:
I checked traces so they wasn’t too close (hopefully) and drillholes.
also I did some changes doing the delay line hack so you can overclock the board.
Adding possability of having both types of oscillators. adding some text etc.
Still GND/VCC planes might be SHIT! I am no hw designer. but hopefully it will WORK!
NOW I ordered some PCBs..
This is a render of the order:
Lets hope it all works.
If you want the gerbers or the sprint file for this:
I assembled it, and it WORKS!’
I haveyet again done some modifications to the board and this I guess will be the FINAL version. Rev 3.3.2
Changes: removed the J100 jumper as the machine did not start without jumpers installed anyway and JT100, same there.
Also for R101, the delayline you can now choose what pad to use for 5 or 10ns delay.
Also added values for all components on the silkscreen.
AND! actually found a function for proper GND/VCC planes, so no more traces but while planes for that.
I used seeedstudio to produce the boards using this:
PCB Dimension – 97.5mm*206.2mm
Surface Finish – ENIG
Min Solder Mask Dam – 0.4mm↑
Copper Weight – 1oz.
Half-cut / Castellated Holes – no
Min Hole Size – 0.3mm
PCB Color – Blue
Material – FR-4 TG130
Layer – 4 layers
Blind Vias – no
PCB Thickness – 1.6
Min Tracking / Spacing – 5/5 mil